---
title: "Jiangsu startup unveils Y10 AI chip promising sub-millisecond robot control"
slug: "jiangsu-startup-unveils-y10-ai-chip-promising-sub-millisecond-robot-co"
date: "2026-10-13"
category: "AI & Automation"
author: "Dr. Kai Wei"
correspondent: "Dr. Kai Wei"
correspondentRole: "Lead Frontier AI Correspondent"
readingTimeMinutes: 1
tags: ["AI","News"]
originalSourceUrl: "https://pandaily.com/y10-physical-ai-chip-1ms-closed-loop-latency-fpga-platform-xu-feixiang"
canonicalUrl: "https://aurav.ae/jiangsu-startup-unveils-y10-ai-chip-promising-sub-millisecond-robot-co"
publisher: "Aura-V Intelligence (aurav.ae)"
---

# Jiangsu startup unveils Y10 AI chip promising sub-millisecond robot control

> A Jiangsu chip startup has announced its Y10 processor, targeting under-1 ms closed-loop latency for industrial robots.

## Key Takeaways (TL;DR)

- Y10 aims for sub-millisecond perception-inference-action loops, addressing latency bottlenecks in physical AI.
- Simulations claim five-fold performance improvement and 80% lower cost versus current x86 + Orin setups.
- An FPGA version is slated for release later this year for industrial robot arm developers.

A Jiangsu chip startup founded in 2025 by former Nvidia GPU architect Xu Feixiang has introduced Y10, a physical-AI processor designed to keep the full perception, inference and action loop under one millisecond — a claim detailed in a [Pandaily interview](https://pandaily.com/y10-physical-ai-chip-1ms-closed-loop-latency-fpga-platform-xu-feixiang). The company says the chip targets industrial robot arms, a segment where existing hardware handles only about 2 % of manual operations on production lines.

Y10 departs from fixed-function ASICs, offering a general-purpose core with a custom, highly programmable instruction set built on the SomaArch architecture. Xu estimates chip architecture contributes roughly 70 % of a parallel processor’s usability, with software accounting for the remaining 30 %.

In internal simulations, Y10 outperforms the x86 + Orin configurations that customers currently use, delivering five times the overall performance at 80 % lower cost. The startup is testing with leading Chinese robot makers and plans to ship an FPGA version of the platform by year-end, allowing developers to evaluate real hardware before silicon tape-out.

---

*Original Think-Tank Source: [Startup Led by Ex-Nvidia GPU Architect Designs Y10 Chip to Close Robot Control Loops in 1 ms](https://pandaily.com/y10-physical-ai-chip-1ms-closed-loop-latency-fpga-platform-xu-feixiang)*